Researcher created a leaderboard of the slowest x86 instructions – record of 198 billion cycles in 62 seconds

Instruction latency analysis usually helps figure out how long low-level commands take to run on a processor, with the goal of optimizing either the architecture itself or applications built for specific hardware.

Hardware researcher Christopher Domas, known as @xoreaxeaxeax on GitHub, decided to flip that idea on its head. His CPU Deoptimization project searches not for the fastest execution of a single assembly instruction, but the slowest.

The winner is fxrstor64, which took 62 seconds, or over 198 billion cycles, to complete. This instruction restores the state of registers used for SIMD calculations from a 512-byte memory area.

To reach such a slow result, Domas first used his own mmiotic tool to find a high-latency area inside the CPU internal PCIe fabric.

He then forced the processor to load a 512-byte state from MMIO (Memory-Mapped I/O), processing each of those bytes as slowly as possible. That step alone took 74 billion cycles, just over 23 seconds.

From there, the researcher pushed further by "starving the fabric while the load is in flight." He used a series of 4-byte reads from another high-latency MMIO register, overwhelming the CPU PCIe root complex and forcing the state restore to queue behind pointless read operations.

The next step involves using the AMX instructions found in Intel Sapphire Rapids architecture for xrstore64. The state area jumps from 512 bytes to 8KB, which could make the instruction hang for over 1 trillion cycles.

The x86 leaderboard is already live on GitHub, and Domas plans to build similar rankings for ARM and RISC-V. A handful of rules apply to submissions – any setup works, but only the execution of a single instruction can be scored.

Interruptible instructions aren't allowed, and neither is scoring emulated instructions run through a handler. All timing gets normalized against the CPU base clock, and every platform ran without hardware modifications.

Since this is all assembly code, the ranking has less to do with the instruction itself and more with what someone actually does with it.

Domas mainly relied on two processors for testing – the Intel Core i7-8559U and AMD Ryzen 7 5800H, the latter inside a Trigkey S5. For the rdmsr instruction, though, he pulled out a VIA Eden chip, part of a line of embedded processors from the early 2000s. The rdmsr command reads a model-specific register, or MSR.

According to Domas, VIA "uses an undocumented register at 0x133 that gives wildly high response time." That instruction took 202 microseconds, or 161,602 cycles, to run.

This isn't the researcher first dive into strange experiments with low-level instructions either. An earlier project called movfuscator is a C compiler that relies solely on the mov (move) command.